Section
Semiconductors
Chip design, foundries, supply chains and export controls.
- TechCrunch ↗
Commonwealth Fusion Systems gets $85M to build better fusion-ready semiconductors
Top-funded fusion startup Commonwealth Fusion Systems received an $85 million award from the federal government to advance conductors for fusion power plants.
- DCD ↗
Vertical Semiconductor awarded $73m in CHIPS Act funding to support vGaN transistor development
The agreement will see the Department of Commerce take a minority stake in the company
- DCD ↗
Aleria to deploy Nvidia Blackwell and Vera Rubin GPUs in US and UAE
Neocloud partners with DDN on deployment
- DCD ↗
US Department of Commerce commits up to $389m in R&D funding to power semiconductors for fusion and advanced computing
Google-backed CFS and Microsoft-backed Helion to receive R&D funding
- Mobile World Live ↗
US pumps $400M into semiconductor R&D
The US Commerce Department awarded $389 million in R&D funding to four companies working on semiconductor development, under the government’s CHIPS and Science Act.
- Mobile World Live ↗
Intel makes construction move on delayed US chip plant
Intel heralded a construction milestone at a long-planned semiconductor manufacturing facility in the US state of Ohio after installing the first major structural truss years after it was announced.
- The Register ↗
To help world gorge on GPUs, Nvidia brings cash bucket to fatten wafer-thin supply chain
Signs Samsung to build substrates, bolsters spend with other players
- The Register ↗
Tens of thousands of Nvidia GPUs sit idle in Meta's Prometheus supercluster, just waiting for a failure
And other fun facts about how Zuckercorp aims to keep a million GPUs running long enough to train a model
- Semiconductor Engineering ↗
A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)
Researchers at Cadence Design Systems and the University of Notre Dame published “A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling.” Abstract: “Accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is…
- Semiconductor Engineering ↗
Thermal Side Channels Create New Security Risks For Autonomous Vehicles (Missouri S&T)
Researchers at Missouri University of Science and Technology published “Can Autonomous Vehicles Keep Their Cool?
- DCD ↗
Intel and Applied Materials to collaborate on chip manufacturing advancements
Work will take place at the companies' respective R&D facilities
- Mobile World Live ↗
Musk plays down TSMC presence at AI fab facility
Elon Musk ruled out Taiwan Semiconductor Manufacturing Company taking an operational role in Terafab, the billionaire’s advanced semiconductor manufacturing facility in the US state of Texas.
- Semiconductor Engineering ↗
Monolithic 3D Memristor-TFT Stack For Programmable Neuromorphic Computing (SNU, Yonsei)
Researchers at Seoul National University and Yonsei University published a technical paper titled “Monolithic three-dimensionally integrated memristor-thin-film transistor for electrically programmable multimode reservoir computing.”…
- Data Center Knowledge ↗
AI Power Spikes Demand Chip-to-Grid Design Changes
AI data centers’ rapid power swings threaten grid stability, requiring coordinated chip-to-grid strategies across chip makers, operators, utilities, and infrastructure providers.
- DCD ↗
Japanese chipmaker Rapidus to establish CORE initiative to support semiconductor design and manufacturing
First phase will see launch of Design Solution Associates project
- Semiconductor Engineering ↗
Chip Industry Technical Paper Roundup: Oct. 6
Low-contact-resistance WSe₂ transistors; backside clock meshes for 2nm GAAFETs; row-parallel processing in DRAM; HBF for high-throughput LLM serving; formal security analysis of CAN XL; abstraction and validation from physical devices to…
- Semiconductor Engineering ↗
Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations
Part 2: Towards scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability.
- Semiconductor Engineering ↗
Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)
Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” Abstract Excerpt: “Clock meshes are used in high-performance…
- Semiconductor Engineering ↗
Reducing Contact Resistance Pushes 2D Transistors Toward Advanced CMOS (HUST, PolyU, UCSB, NUS)
Researchers at Huazhong University of Science and Technology, Hong Kong Polytechnic University, University of California, Santa Barbara, and National University of Singapore published a technical paper titled “Low contact resistance and…
- Network World ↗
New memory player CXMT begins mass production of DRAM platform
Chinese memory-chip manufacturer ChangXin Memory Technologies (CXMT) has begun mass production of its fifth-generation DRAM technology platform, marking another step in the company’s effort to stand alongside the big three memory makers…
- DCD ↗
Elon Musk confirms TeraFab discussions between SpaceX and TSMC, says SpaceXAI will be renamed SpaceXSI
Follows reports that TSMC is mulling over plans for a chip manufacturing hub in Texas
- Semiconductor Engineering ↗
Extreme Environments Push Chips To Their Breaking Point
Orbital data centers, defense systems, quantum computing, particle physics, and advanced manufacturing are raising the bar for simulation, test, and lab tools.
- Semiconductor Engineering ↗
The Proof Economy
As artificial intelligence makes creation abundant, proof becomes the new scarcity.